Time-to-digital converter calibration
US11569831B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2022 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | Mar 23, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/378
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase-locked loop (DPLL) may include a time-to-digital converter (TDC) to provide a phase error signal, a frequency-divider to perform frequency division on an output signal to generate a frequency-divided output signal, a delta-sigma-modulator (DSM) to provide a test signal that represents a quantization error of the DSM, and a digital-to-time converter (DTC) to at least partially remove the quantization error from the frequency-divided output signal based on the test signal to generate the feedback signal. The DPLL may include a circuit to cause the DTC to provide a percentage of the quantization error such that the percentage of the quantization error is in the phase error signal, and a TDC calibration component to calibrate the TDC by applying a gain adjustment factor to the TDC. The gain adjustment factor may be based on the test signal and the phase error signal including the percentage of the quantization error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.