Baud-rate clock recovery lock point control
US11569975B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 28, 2021 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | May 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4917
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A baud-rate phase detector uses two error samplers. One error sampler is used to determine whether the sampling time is too early error detection. The other is used to determine whether sampling time is too late. The early error sampler is configured to use a first threshold voltage. The late error sampler is configured to use a second threshold voltage. By adjusting the voltage difference between the first threshold voltage and the second threshold voltage, the phase difference between the local timing reference clock and the transitions of the data signal may be adjusted. The phase difference between the local timing reference clock and the transitions of the data signal may be adjusted to improve or optimize a desired receiver characteristic such as bit error rate or signal eye opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.