Integrated sensor with reduced skew

US11573180B2 · kind B2 · utility

Assignee

• Quantum-Si Incorporated · US

Inventors

• Eric A. G. Webster · Mountain View, US
• Dajiang Yang · San Jose, US
• Xin Wang · San Jose, US
• Zhaoyu He · Milpitas, US
• Changhoon Choi · Palo Alto, US
• Peter J. Lim · Saratoga, US
• Todd Rearick · Cheshire, US

Key dates

• Filing date: Apr 7, 2021
• Grant date: Feb 7, 2023
• Expiry date: Apr 7, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G01N2021/6439
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.