Memory cell level assignment using optimal level permutations in a non-volatile memory
US11573715B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Mar 1, 2021 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | Apr 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5644
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to manage the memory device using a cell level assignment with respect to a plurality of memory cell levels, determine a cell count for each of the cell levels associated with original data of the memory device that is to be accessed, predict an error rate from the cell counts, and selectively adjust the cell level assignment based on the error rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.