Built-in self-test for a programmable vision accelerator of a system on a chip
US11573921B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2021 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | Aug 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.