Yen-Te Shih
17Patents
2h-index
6Co-inventors
43Inventor score
Filing activity: Jun 20, 2013 → Jan 6, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11593290B1 | Using a hardware sequencer in a direct memory access system of a system on a chip | Physics | 3 | Active |
| US11573795B1 | Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chip | Physics | 3 | Active |
| US11573921B1 | Built-in self-test for a programmable vision accelerator of a system on a chip | Electricity | 2 | Active |
| US11934829B2 | Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chip | Physics | 1 | Active |
| US11593001B1 | Using per memory bank load caches for reducing power use in a system on a chip | Physics | 1 | Active |
| US11704067B2 | Performing multiple point table lookups in a single cycle in a system on chip | Physics | 1 | Active |
| US11636063B2 | Hardware accelerated anomaly detection using a min/max collector in a system on a chip | Physics | 1 | Active |
| US11836527B2 | Accelerating table lookups using a decoupled lookup table accelerator in a system on a chip | Physics | 0 | Active |
| US11954496B2 | Reduced memory write requirements in a system on a chip using automatic store predication | Physics | 0 | Active |
| US12118353B2 | Performing load and permute with a single instruction in a system on a chip | Physics | 0 | Active |
| US12093539B2 | Using per memory bank load caches for reducing power use in a system on a chip | Physics | 0 | Active |
| US12099439B2 | Performing load and store operations of 2D arrays in a single cycle in a system on a chip | Physics | 0 | Active |
| US9088740B2 | System and method of reducing noise | Electricity | 0 | Active |
| US12204475B2 | Using a hardware sequencer in a direct memory access system of a system on a chip | Physics | 0 | Active |
| US11940947B2 | Hardware accelerated anomaly detection using a min/max collector in a system on a chip | Physics | 0 | Active |
| US9042643B2 | Method for demosaicking | Electricity | 0 | Active |
| US12050548B2 | Built-in self-test for a programmable vision accelerator of a system on a chip | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.