Electronic design tracing and tamper detection using automatically generated layout patterns
US11574111B1 · kind B1 · utility
1Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2020 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | Dec 31, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/532
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are method(s), system(s), and article(s) of manufacture for implementing an approach to facilitate traceability and tamper detection of electronic designs. This approach allows for tracing and tamper detection at any stage of design and manufacturing, such as during layout generation, post-design, post-mask, and post manufacturing of the electronic designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.