Memory devices configured to generate pulse amplitude modulation-based DQ signals, memory controllers, and memory systems including the memory devices and the memory controllers
US11574662B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2021 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | Jun 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01742
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device as provided may apply a pulse amplitude modulation method to data (DQ) signal transmission/reception and may scale a DQ signal according to an operating frequency condition, so as to improve data transmission performance and effectively improve power consumption. The memory device includes a memory cell array, and a data input/output circuit configured to scale a DQ signal that includes data read from the memory cell array and output the scaled DQ signal. The data input/output circuit is configured to scale the DQ signal based on an n-level pulse amplitude modulation (PAMn) (where n is 4 or a greater integer) with a DQ parameter that corresponds an operating frequency condition and output the DQ signal. Other aspects include memory controllers that communicate with the memory devices, and memory systems that include the memory devices and memory controllers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.