Data latch circuit and semiconductor memory device
US11574663B2 · kind B2 · utility
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5References
8Claims
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Key dates
| Filing date | Dec 2, 2020 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | Mar 6, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.