Neuromorphic memory circuit and method of neurogenesis for an artificial neural network
US11574679B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2022 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | May 4, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit configured to perform multiply-accumulate (MAC) operations for performance of an artificial neural network includes a series of synapse cells arranged in a cross-bar array. Each cell includes a memory transistor connected in series with a memristor. The memory circuit also includes input lines connected to the source terminal of the memory transistor in each cell, output lines connected to an output terminal of the memristor in each cell, and programming lines coupled to a gate terminal of the memory transistor in each cell. The memristor of each cell is configured to store a conductance value representative of a synaptic weight of a synapse connected to a neuron in the artificial neural network, and the memory transistor of each cell is configured to store a threshold voltage representative of a synaptic importance value of the synapse connected to the neuron in the artificial neural network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.