Package architecture utilizing photoimageable dielectric (PID) for reduced bump pitch
US11574874B2 · kind B2 · utility
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3References
20Claims
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Key dates
| Filing date | Mar 30, 2017 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | Oct 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.