Lauren A. Link
17Patents
1h-index
27Co-inventors
46Inventor score
Filing activity: Mar 30, 2017 → Jan 3, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10700021B2 | Coreless organic packages with embedded die and magnetic inductor structures | Electricity | 2 | Active |
| US11189409B2 | Electronic substrates having embedded dielectric magnetic material to form inductors | Electricity | 1 | Active |
| US11251113B2 | Methods of embedding magnetic structures in substrates | Electricity | 1 | Active |
| US11552008B2 | Asymmetric cored integrated circuit package supports | Electricity | 1 | Active |
| US10741947B2 | Plated through hole socketing coupled to a solder ball to engage with a pin | Electricity | 1 | Active |
| US11335632B2 | Magnetic inductor structures for package devices | Electricity | 0 | Active |
| US11705389B2 | Vias for package substrates | Electricity | 0 | Active |
| US11651902B2 | Patterning of thin film capacitors in organic substrate packages | Electricity | 0 | Active |
| US11610706B2 | Release layer-assisted selective embedding of magnetic material in cored and coreless organic substrates | Electricity | 0 | Active |
| US11289263B2 | Electronic substrates having embedded magnetic material using photo-imagable dielectric layers | Electricity | 0 | Active |
| US11444042B2 | Magnetic structures in integrated circuit packages | Electricity | 0 | Active |
| US11205626B2 | Coreless organic packages with embedded die and magnetic inductor structures | Electricity | 0 | Active |
| US11574874B2 | Package architecture utilizing photoimageable dielectric (PID) for reduced bump pitch | Electricity | 0 | Active |
| US11075130B2 | Package substrate having polymer-derived ceramic core | Electricity | 0 | Active |
| US11862552B2 | Methods of embedding magnetic structures in substrates | Electricity | 0 | Active |
| US11881463B2 | Coreless organic packages with embedded die and magnetic inductor structures | Electricity | 0 | Active |
| US11824013B2 | Package substrate with reduced interconnect stress | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.