Cryptographic computing engine for memory load and store units of a microarchitecture pipeline
US11575504B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2020 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | Feb 16, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor comprises a first register to store an encoded pointer to a memory location. First context information is stored in first bits of the encoded pointer and a slice of a linear address of the memory location is stored in second bits of the encoded pointer. The processor also includes circuitry to execute a memory access instruction to obtain a physical address of the memory location, access encrypted data at the memory location, derive a first tweak based at least in part on the encoded pointer, and generate a keystream based on the first tweak and a key. The circuitry is to further execute the memory access instruction to store state information associated with memory access instruction in a first buffer, and to decrypt the encrypted data based on the keystream. The keystream is to be generated at least partly in parallel with accessing the encrypted data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.