Page buffer circuit with bit line select transistor
US11581045B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2021 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Mar 3, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure provide a memory device. For example, the memory device can include a memory array, a bitline and a buffer. The memory array can include a plurality of memory strings. The memory strings can be divided into a first memory string group and a second memory string group. The bitline can include a first bitline segment coupled to the first memory string group and a second bitline segment coupled to the second memory string group. The first bitline segment can be disposed between the first memory string group and the buffer and be connected to the buffer through a first conduction path. The second bitline segment can be disposed between the second memory string group and the buffer and be connected to the buffer through a second conduction path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.