Memory device test mode access
US11581053B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2020 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | May 11, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.