Methods to pattern TFC and incorporation in the ODI architecture and in any build up layer of organic substrate

US11581271B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Rahul Jain · Chandler, US
• Kyu Oh Lee · Chandler, US
• Islam A. Salama · Scottsdale, US
• Amruthavalli Pallavi Alur · Tempe, US
• Wei-Lun Kane Jen · Chandler, US
• Yongki Min · Phoenix, US
• Sheng Li · Santa Clara, US

Key dates

• Filing date: Mar 14, 2019
• Grant date: Feb 14, 2023
• Expiry date: Jun 13, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2224/18
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.