Patent · US Active

Multi-chip package

US11581289B2 · kind B2 · utility

0Cited by

2References

19Claims

0Family size

Assignee

STMICROELECTRONICS PTE LTD · SG

Inventors

Yong Chen · 林湖乡, CN
David Gani · Seletar Hills, SG

Key dates

Filing date	Jul 21, 2020
Grant date	Feb 14, 2023
Priority date	—
Expiry date	Jul 30, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/117
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.