Memory devices having cell over periphery structure, memory packages including the same, and methods of manufacturing the same
US11581297B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2020 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Jun 1, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.