Memory device, integrated circuit device and method
US11581368B2 · kind B2 · utility
2Cited by
0References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 15, 2020 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Jan 1, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes at least one bit line, at least one word line, and at least one memory cell. The memory cell includes a first transistor, a plurality of data storage elements, and a plurality of second transistors corresponding to the plurality of data storage elements. The first transistor includes a gate electrically coupled to the word line, a first source/drain, and a second source/drain. Each data storage element among the plurality of data storage elements and the corresponding second transistor are electrically coupled in series between the first source/drain of the first transistor and the bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.