Gate-all-around integrated circuit structures having depopulated channel structures

US11581404B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Tanuj Trivedi · Hillsboro, US
• Jeong Dong Kim · Scappoose, US
• Walid M. Hafez · Portland, US
• Hsu-Yu Chang · Hillsboro, US
• Rahul Ramaswamy · Portland, US
• Ting Chang · Portland, US
• Babak Fallahazad · Portland, US

Key dates

• Filing date: May 5, 2021
• Grant date: Feb 14, 2023
• Expiry date: May 5, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/28568
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.