Translation device, test system including the same, and memory system including the translation device
US11581960B2 · kind B2 · utility
1Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2021 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Jul 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0016
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A translation device, a test system, and a memory system are provided. The translation device includes plural first input/output (I/O) circuits that respectively transmit and receive first signals through plural pins based on a pulse amplitude modulation (PAM)-M mode, a second I/O circuit that transmits and receives a second signal through one or more pins based on a PAM-N mode, and a translation circuit that translates the first signals into the second signal and translates the second signal into the first signals. M and N are different integers of 2 or more.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.