Patent · US Active

Fine resolution on-chip voltage simulation to prevent under voltage conditions

US11586267B2 · kind B2 · utility

0Cited by

5References

18Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Thomas Strach · Wildberg, DE
Preetham M. Lobo · Bengaluru, IN
Tobias Webel · Eppelheim, DE

Key dates

Filing date	Dec 19, 2018
Grant date	Feb 21, 2023
Priority date	—
Expiry date	Dec 22, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH02H3/247
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments of the present disclosure relate to managing power provided to a semiconductor circuit to prevent undervoltage conditions. A measured voltage value describing a measured supply voltage at a first subcircuit of a semiconductor circuit can be received, the measured voltage value having a first resolution. A selected metric indicative of a supply voltage present at the first subcircuit can be received, the selected metric having a second resolution higher than the first resolution. The selected metric is calibrated to obtain a calibrated metric when a transition of the measured voltage value occurs.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.