Method, apparatus, and system for run-time checking of memory tags in a processor-based system
US11586537B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2021 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Aug 4, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a store datapath configured to perform tag checking in a store operation to a store address associated with a cache line in a memory. The store datapath includes a cache lookup circuit configured to pre-load a store cache line that is to be updated in the store operation, wherein the store cache line comprises the cache line in the memory to be updated in the store operation. The store datapath also includes a tag check circuit configured to compare a store address tag associated with the store address to a store operation tag associated with the store operation. The data processing system may include a load datapath configured to perform tag checking in a load operation from a load cache line in the memory by comparing a load address tag associated with the load address to a load operation tag associated with the load operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.