Address/command chip controlled data chip address sequencing for a distributed memory buffer system
US11587600B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2019 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Jan 9, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. The memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.