Integrated circuit with embedded memory modules
US11587636B2 · kind B2 · utility
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2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2021 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Dec 15, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to a system and method for maintaining stability during a scan shift operation on multiple embedded memories in an integrated circuit. Examples disclosed herein include an integrated circuit comprising a plurality of memory modules and a built-in self-test controller, wherein the BIST controller and memory modules are arranged and configured to reduce toggling of cells in the memory modules during a scan shift operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.