Integrated electronic device with a redistribution region and a high resilience to mechanical stresses and method for its preparation
US11587866B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2020 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Oct 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an integrated electronic device including a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A hole is formed extending into the frontal surface and through the frontal dielectric layer. A conductive region is formed in the hole. A barrier layer is formed in the hole and extends into the hole. A first coating layer covers a top and sides of a redistribution region of the conductive region and a second coating layer covers is formed covering the first coating layer. A capillary opening is formed extending into the first and second coating layers to the barrier layer. A cavity is formed between the redistribution region and the frontal surface and is bounded on one side by the first coating layer and on the other by the barrier structure by passing an aqueous solution through the capillary opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.