Semiconductor memory device
US11587929B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2020 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | May 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/84
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.