Fin field-effect transistor and method of forming the same
US11588041B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2020 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Nov 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
A method for manufacturing a semiconductor device includes forming a gate trench over a semiconductor fin, the gate trench including an upper portion and a lower portion. The method includes sequentially forming one or more work function layers, a capping layer, and a glue layer over the gate trench. The glue layer includes a first sub-layer and a second sub-layer that have respective different etching rates with respect to an etching solution. The method includes removing the second sub-layer while leaving a first portion of the first sub-layer filled in the lower portion of the gate trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.