Communication chip
US11588612B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2021 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Oct 20, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/20
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A communication chip includes an input port, a gain circuit, a correction circuit having a phase-locked loop (PLL) circuit and a return terminal, a post-processing circuit, and a switching circuit. The gain circuit includes an input terminal and a quadrature modulation circuit that operates according to a reference clock. The gain circuit gains a signal from the input terminal according to a bias voltage and outputs a gained signal. The PLL circuit generates a correction signal through synchronization according to the reference clock. The post-processing circuit obtains an input signal strength according to a correction table and a signal from a receiving terminal of the post-processing circuit. The switching circuit couples the correction signal to the input terminal and the gained signal to the return terminal in test mode and couples the input port to the input terminal and the gained signal to the receiving terminal in an operating mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.