Sharing instruction cache footprint between multiple threads
US11593108B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2021 |
| Grant date | Feb 28, 2023 |
| Priority date | — |
| Expiry date | Aug 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects are provided for sharing instruction cache footprint between multiple threads. A set/way pointer to an instruction cache line is derived from a system memory address associated with an instruction fetch from a memory page. It is determined that the instruction cache line is shareable between a first thread and a second thread. An alias table entry is created indicating that other instruction cache lines associated with the memory page are also shareable between threads. Another instruction fetch is received from another thread requesting an instruction from another system memory address associated with the memory page. A further set/way pointer to another instruction cache line is derived from the other system memory address. It is determined that the other instruction cache line is shareable based on the alias table entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.