Glitch power analysis with register transfer level vectors
US11593543B2 · kind B2 · utility
1Cited by
2References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 4, 2021 |
| Grant date | Feb 28, 2023 |
| Priority date | — |
| Expiry date | Mar 4, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes acquiring a vector data signal associated with a circuit design, performing a timing update to determine timing information for the circuit design, and identifying a glitch in the circuit design based on a shifted vector waveform. The timing information includes a signal delay associated with a cell of the circuit design. The shifted vector waveform is generated by shifting the vector data signal based on the timing information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.