Chopper stabilized analog multiplier unit element with binary weighted charge transfer capacitors
US11593573B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2021 |
| Grant date | Feb 28, 2023 |
| Priority date | — |
| Expiry date | Jul 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Unit Element (UE) has a positive UE and a negative UE, each having a digital X input and a digital W input with a sign bit, the sign bit is exclusive ORed with a chop clock to generate a chopped sign bit. The positive UE is enabled when the chopped sign bit is positive and the negative UE is enabled when the chopped sign bit is negative. Each positive and negative UE comprises groups of NAND gates generating an output and complementary output which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The NAND gate outputs and complementary outputs are coupled through binary weighted charge transfer capacitors the positive charge transfer line and negative charge transfer line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.