Operating method for semiconductor circuit
US11594266B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2021 |
| Grant date | Feb 28, 2023 |
| Priority date | — |
| Expiry date | Mar 9, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD′.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.