Memory device for receiving one clock signal as a multi-level signal and restoring original data encoded into the clock signal and method of operating the same
US11594267B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2021 |
| Grant date | Feb 28, 2023 |
| Priority date | — |
| Expiry date | Apr 14, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a memory device including receiving a multilevel signal having M levels transmitted by an external controller through a clock receiving pin, where M is a natural number greater than 2, and decoding the multilevel signal to restore at least one of Data Bus Inversion (DBI) data, Data Mask (DM) data, Cyclic Redundancy Check (CRC) data, or Error Correction Code (ECC) data may be provided. The multilevel signal is a clock signal transmitted by the external controller, and is a signal swinging based on an intermediate reference signal that is an intermediate value between a minimum level and a maximum level among the M levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.