Memory cell driver, memory cell arrangement, and methods thereof

US11594271B2 · kind B2 · utility

Assignee

• Ferroelectric Memory GmbH · DE

Inventors

• Marko Noack · Dresden, DE
• Rolf Jähne · Dresden, DE

Key dates

• Filing date: Apr 29, 2020
• Grant date: Feb 28, 2023
• Expiry date: May 22, 2040

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/2297
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In various embodiments, a memory cell arrangement is provided including a memory cell driver and one or more memory cells, wherein one or more control nodes of each of the one or more memory cells are electrically conductively connected to one or more output nodes of the memory cell driver. The memory cell driver may include: a first supply node to receive a first supply voltage and a second supply node to receive a second supply voltage, a plurality of input nodes to receive a plurality of input voltages, one or more output nodes, and a logic circuit connected to the first supply node, the second supply node, the plurality of input nodes, and the one or more output nodes, wherein the logic circuit includes one or more logic gates and is configured to connect via the one or more logic gates either the first supply node or the second supply node to the one or more output nodes in response to the plurality of input voltages.