Self-adjustable self-timed dual-rail SRAM
US11594276B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2020 |
| Grant date | Feb 28, 2023 |
| Priority date | — |
| Expiry date | Aug 4, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual-rail memory includes, in part, a memory array that operates using a first supply voltage, and a periphery circuit that operates using a second supply voltage. The periphery circuit includes, in part, a clock generation circuit and a comparator. The dual-rail memory also includes a level shifter that varies the voltage level of a number of signals of the memory between the first and second supply voltages. The clock generation circuit is adapted, among other operations, to generate a read clock signal in response to a read request signal. The level shifter is adapted to supply a reference wordline read signal in response to the read clock signal. The comparator is adapted to select a delay between the read clock signal and the reference wordline read signal in response to a difference between the first and second supply voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.