Semiconductor package
US11594499B2 · kind B2 · utility
0Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2021 |
| Grant date | Feb 28, 2023 |
| Priority date | — |
| Expiry date | Mar 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.