Computation-in-memory in three-dimensional memory device
US11594531B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2021 |
| Grant date | Feb 28, 2023 |
| Priority date | — |
| Expiry date | Jul 5, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Three-dimensional (3D) memory devices are provided. An exemplary 3D memory device includes a first semiconductor structure including a peripheral circuit, a data processing circuit, and a first bonding layer including a plurality of first bonding contacts. The peripheral circuit and the data processing circuit are stacked over one another vertically on different planes. The 3D memory device also includes a second semiconductor structure including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts. In addition, the 3D memory device includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.