Memory tiering techniques in computing systems
US11599415B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2021 |
| Grant date | Mar 7, 2023 |
| Priority date | — |
| Expiry date | Aug 12, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/305
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques of memory tiering in computing devices are disclosed herein. One example technique includes retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.