Memory circuit architecture

US11600307B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• David Li · San Diego, US
• Rahul Biradar · Kalaburagi, IN
• Biju Manakkam Veetil · Bengaluru, IN
• Po-Hung Chen · Taipei, TW
• Ayan Paul · San Diego, US
• Sung Son · San Jose, US
• Shivendra Kushwaha · Kanchinakote, IN
• Ravindra Reddy Chekkera · Vemula, IN
• Derek Yang · Poway, US

Key dates

• Filing date: Dec 29, 2020
• Grant date: Mar 7, 2023
• Expiry date: Dec 29, 2040

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C8/14
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.