Rahul Biradar
5Patents
1h-index
11Co-inventors
37Inventor score
Filing activity: Aug 25, 2020 → Feb 1, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11600307B2 | Memory circuit architecture | Physics | 1 | Active |
| US11251123B1 | Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines, and related methods | Electricity | 0 | Active |
| US11908537B2 | Memory circuit architecture | Physics | 0 | Active |
| US11289495B1 | Static random access memory (SRAM) bit cell circuits with a minimum distance between a storage circuit active region and a read port circuit active region to reduce area and SRAM bit cell array circuits | Electricity | 0 | Active |
| US11222846B1 | Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines, and related methods | General | 0 | Revoked |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.