Self-aligned contacts
US11600524B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2021 |
| Grant date | Mar 7, 2023 |
| Priority date | — |
| Expiry date | Mar 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/665
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.