Low frequency power supply spur reduction in clock signals
US11604490B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2021 |
| Grant date | Mar 14, 2023 |
| Priority date | — |
| Expiry date | Oct 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17784
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques and apparatus for reducing low frequency power supply spurs in clock signals. One example circuit generally includes a first power supply circuit configured to generate a first power supply voltage on a first power supply rail, a second power supply circuit configured to generate a second power supply voltage on a second power supply rail, a clock distribution network, and a feedback circuit coupled between the second power supply rail and at least one input of the first power supply circuit. The feedback circuit may be configured to sense the second power supply voltage, to process the sensed second power supply voltage, and to output at least one feedback signal to control the first power supply circuit based on the processed second power supply voltage. The clock distribution network may include first and second sets of clock drivers powered by the first and second power supply voltages, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.