Processor security mode based memory operation management
US11604505B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2020 |
| Grant date | Mar 14, 2023 |
| Priority date | — |
| Expiry date | May 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7807
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments include methods and devices for system on chip infrastructure of system on chip infrastructure secure memory access and power management. Some embodiments, include determining whether a processor is performing a secure memory access transaction, and gating a clock signal from being transmitted to a secure portion of a memory in response to determining that the processor is not performing a secure memory access transaction. Some embodiments include determining whether any processor is operating in a secure mode, and transmitting a retention signal to the secure portion of the memory in response to determining that no processor is operating in a secure mode. The retention signal may be configured to set a retention state for the secure portion of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.