Processor comprising a double multiplication and double addition operator actuable by an instruction with three operand references
US11604646B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2021 |
| Grant date | Mar 14, 2023 |
| Priority date | — |
| Expiry date | Dec 29, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3013
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of processing data by a processor, the method comprising the steps of: receiving, by the processor, an instruction including an operator code associated with three register references designating registers configured to contain pairs of multiplication operands, an addition operand, and a result register configured to receive an operator result, the operator code designating an operator configured to compute products of the pairs of multiplication operands and add the products with the addition operand; decoding the instruction by an instruction decoder of the processor, to determine the operator to be executed, and the registers containing the operands to be supplied to the operator and the result of the operator; actuating the operator by an arithmetic circuit of the processor, consuming the operands in the registers designated by the register references; and storing the result of the operator in the designated result register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.