Memory device with write pulse trimming
US11605427B2 · kind B2 · utility
1Cited by
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20Claims
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Assignee
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Key dates
| Filing date | Jan 4, 2021 |
| Grant date | Mar 14, 2023 |
| Priority date | — |
| Expiry date | Jan 4, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.