Memory cell, method of forming the same, and semiconductor die
US11605779B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2021 |
| Grant date | Mar 14, 2023 |
| Priority date | — |
| Expiry date | Feb 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
Abstract
Provided are a memory cell and a method of forming the same. The memory cell includes a first dielectric pattern, a second dielectric pattern, a first bottom electrode, a first storage pattern, and a first top electrode. The first bottom electrode is disposed between the first dielectric pattern and the second dielectric pattern, and the first bottom electrode interfaces a first sidewall of the first dielectric pattern and a sidewall of the second dielectric pattern. The first storage pattern is disposed on the first dielectric pattern, the second dielectric pattern and the first bottom electrode, wherein the first storage pattern is electrically connected to the first bottom electrode. The first storage pattern is between the first bottom electrode and the first top electrode. A semiconductor die including a memory array is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.