Low etch pit density, low slip line density, and low strain indium phosphide
US11608569B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2021 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Mar 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
Methods and wafers for low etch pit density, low slip line density, and low strain indium phosphide are disclosed and may include an indium phosphide single crystal wafer having a diameter of 4 inches or greater, having a measured etch pit density of less than 500 cm−2, and having fewer than 5 dislocations or slip lines as measured by x-ray diffraction imaging. The wafer may have a measured etch pit density of 200 cm−2 or less, or 100 cm−2 or less, or 10 cm−2 or less. The wafer may have a diameter of 6 inches or greater. An area of the wafer with a measured etch pit density of zero may at least 80% of the total area of the surface. An area of the wafer with a measured etch pit density of zero may be at least 90% of the total area of the surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.