Systems and methods to load a tile register pair

US11609762B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Raanan Sade · Migdal HaEmek, IL
• Simon Rubanovich · Haifa, IL
• Amit Gradstein · Binyamina - Givat Ada, IL
• Zeev Sperber · Jerusalem, IL
• Alexander Heinecke · San Jose, US
• Robert Valentine · Kiryat Tivon, IL
• Mark J. Charney · Lexington, US
• Bret L. Toll · Hillsboro, US
• Jesus Corbal · King City, US
• Elmoustapha Ould-Ahmed-Vall · Chandler, US
• Menachem Adelman · Haifa, IL

Key dates

• Filing date: Aug 10, 2021
• Grant date: Mar 21, 2023
• Expiry date: Aug 10, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/30014
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Embodiments detailed herein relate to systems and methods to load a tile register pair. In one example, a processor includes: decode circuitry to decode a load matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, respectively, each matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded load matrix pair instruction to load every element of left and right tiles of the identified destination matrix from corresponding element positions of left and right tiles of the identified source matrix, respectively, wherein the executing operates on one row of the identified destination matrix at a time, starting with the first row.