Memory system
US11609814B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2021 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Jul 28, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a semiconductor storage device and a memory controller including a storage circuit that stores correction value for read voltages in association with the word line, and a control circuit that reads data from the memory cells, performs a correction operation on the read data to determine a number of error bits therein, determines the correction value for each read voltage based on the number of error bits and a ratio of a lower tail fail bit count and an upper tail fail bit count, and stores the correction values for the read voltages in the storage circuit. The lower tail fail bit count represents the number of memory cells in a first state having threshold voltages of an adjacent state, and the upper tail fail bit count represents the number of memory cells in the adjacent state having threshold voltages of the first state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.